tag:blogger.com,1999:blog-8531143406441550247.post1450473342825518168..comments2023-10-15T14:19:30.494+02:00Comments on SDR with BladeRF: First VHDL-attempts to remove DC from BladeRF-outputsAnonymoushttp://www.blogger.com/profile/11105029365495152717noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-8531143406441550247.post-4709411435086007802014-03-30T14:15:17.128+02:002014-03-30T14:15:17.128+02:00HDL's only allow you to drive a signal from a ...HDL's only allow you to drive a signal from a single process so it understands from a very narrow context what the next value should be.<br /><br />The errors are just saying that you assign the signal 'rx_average_i' in two separate processes - one in the 'rx_sample' process, and the other in the 'average' process. You can use 'rx_average_i' in any process, but only assign to it in a single process.<br /><br />Also, your 'count' variable in the 'average' process is just an integer. By default, VHDL will make all integers 32 bits. You should constrain your integers if you know you won't be using them. To do that you type 'variable count : integer range 0 to 127;'. Also note that integer is signed, natural is 0 and higher, and positive is 1 and higher. They can all be compared to each other, but the extra limits may be helpful for you.<br /><br />In general, VHDL is a very strict language. You will get a lot of compilation errors before things will attempt to even simulate. Speaking of which, I highly recommend you get ModelSim from Altera and simulate your algorithm you plan on using. It's much, much easier in a simulation environment to verify it is doing what you expect.<br /><br />Good luck!Brianhttps://www.blogger.com/profile/09270339172406238044noreply@blogger.com